|
BASIS FOR COMPARISON |
RISC |
CISC |
|
Emphasis on |
Software |
Hardware |
|
Includes |
Single clock |
Multi-clock |
|
Instruction-set size |
Small |
Large |
|
Instruction formats |
fixed (32-bit)
format |
Varying formats
(16-64 bits each instruction). |
|
Addressing modes
used |
Limited to 3-5 |
12-24 |
|
General purpose
registers used |
32-192 |
8-24 |
|
Memory inferences |
Register to register |
Memory to memory |
|
Cache design |
Split data cache and
instruction cache. |
Unified cache for
instructions and data. |
|
Clock rate |
50-150 MHz |
33-50 MHz |
|
Cycles Per Instruction |
Single cycle for all
instructions and an average CPI < 1.5. |
CPI between 2 and
15. |
|
CPU Control |
Hardwired without
control memory. |
Micro-coded using
control memory (ROM). |
