RISC Vs CISC

 

BASIS FOR COMPARISON	RISC	CISC
Emphasis on	Software	Hardware
Includes	Single clock	Multi-clock
Instruction-set size	Small	Large
Instruction formats	fixed (32-bit) format	Varying formats (16-64 bits each instruction).
Addressing modes used	Limited to 3-5	12-24
General purpose registers used	32-192	8-24
Memory inferences	Register to register	Memory to memory
Cache design	Split data cache and instruction cache.	Unified cache for instructions and data.
Clock rate	50-150 MHz	33-50 MHz
Cycles Per Instruction	Single cycle for all instructions and an average CPI < 1.5.	CPI between 2 and 15.
CPU Control	Hardwired without control memory.	Micro-coded using control memory (ROM).

 

Master Slave Flip Flop

Basically, this type of flip flop can be designed with two JK FFs by connecting in series. One of these FFs, one FF works as the master as well as other FF works as a slave. The connection of these FFs can be done like this, the master FF output can be connected to the inputs of the slave FF. Here slave FF’s outputs can be connected to the inputs of the master FF.

In this type of FF, an inverter is also used addition to two FFs. The inverter connection can be done in such a way that where the inverted CLK pulse can be connected to the slave FF. In other terms, if CLK pulse is 0 for a master FF, then CLK pulse will be 1 for a slave FF. Similarly, when CLK pulse is 1 for master FF, then CLK pulse will be 0 for slave FF.

 

Master-Slave FF Working

Whenever the CLK pulse goes to high which means 1, then the slave can be separated; the inputs like J & K may change the condition of the system.

The slave FF can be is detached until the CLK pulse goes to low which means to 0. Whenever the CLK pulse goes back to low-state, then the data can be transmitted from the master FF to the slave FF and finally, the o/p can be obtained.

At first, the master FF will be triggered at a positive level whereas the slave FF will be triggered at a negative level. Due to this reason, the master FF responds first.

If J=0 & K=1, then the output of the master FF ‘Q’ goes to the input K of the slave FF & the CLK forces the slave FF to RST (reset), therefore the slave FF copies the master FF.

If J=1 & K=0, then the of the master FF ‘Q’ goes to the input J of the slave FF & the CLK’s negative transition sets the slave FF, and copies the master.

If J=1 & K=1, then it toggles over the CLK’s positive transition & therefore the slave toggles over the CLK’s negative transition.

If both the J & K are 0, then the FF can be immobilized & Q remains unmovable.